Magnetoresistive random-access memory (MRAM) is a non-volatile random-access memory technology that has been recognized to potentially meet the demands for continued increases in density of existing memory technologies, notably flash RAM and DRAM. A Magnetic Tunnel Junction (MTJ)-based MRAM device includes arrays of MTJ-based memory cells which can store data in the magnetization orientation between ferromagnetic layers of the MTJ in each cell.
More specifically, an MTJ includes three essential layers: a free layer, a tunneling barrier layer, and a pinned layer. The free layer and the pinned layer are ferromagnetic layers, the tunneling barrier layer is a thin insulator layer located in-between. In the free layer, the magnetization direction is free to rotate; whereas, the magnetization of the pinned layer is fixed and therefore this layer is also referred as the “fixed layer.” An anti-ferromagnetic layer may be used to fix, or pin, the magnetization of the pinned layer in a particular direction. A data bit is written to the MTJ by changing the magnetization direction of one of the ferromagnetic plates of the magnetic element. The orientations of the magnetic moments of the free layer and the pinned layer determine the resistance of the MTJ which dictates the bit value of the memory cell, “0” or “1.”
Spin torque transfer (STT) is a technique for writing to MTJ-based memory cells. When a spin-polarized current (most of the electrons of the current have spins aligned in the same direction) is applied to a free ferromagnetic layer, the electrons may get repolarized on account of the orientation of the magnetic moments of the free layer. The free layer experiences a torque associated with the change in the angular momentum of the electrons as they are repolarized. If the current density is high enough, this torque has enough energy to switch the magnetization direction of the free layer. As a result, the bit data represented by the memory cell can switch between “1” and “0.” The advantages of using STT for writing to magnetic elements have been well established, including smaller bit size, fewer process steps, better scalability for large arrays, and lower writing current requirements, as compared with other writing techniques.
Depending on the orientation of the magnetic anisotropy of the fixed layers, there are two main types of MTJs used in MRAM, perpendicular MTJs and in-plane MTJs. In a perpendicular MTJ, the magnetic anisotropy of the fixed layer is generally perpendicular to the planes of fixed layer and the substrate surface; whereas in an in-plane MTJ, the magnetic anisotropy of the fixed layer is generally parallel to the planes of fixed layer and the substrate surface.
Fabrication of MTJ-based memory cells involves complex processing procedures, including formation of a stack of multiple layers of various films and several annealing steps. Particularly, after a fixed layer is deposited on a Silicon substrate and etched into pillars for individual MTJ cells, the substrate undergoes a magnetic annealing process to magnetize the fixed layer pillars. For example, the magnetic annealing process is executed in a furnace (or an annealing chamber) under vacuum at an elevated temperature by using a predetermined external magnetic field.
During such a magnetic annealing process, it is critical that the features on the substrate are uniformly and consistently subject to the temperature and magnetic field as defined in a processing recipe. Practically, limited by the overall size of the annealing equipment, the magnetic field and the temperature distribution in the annealing chamber can only be optimized for a relatively small center region yet sufficient to encompass the processing zone. A cassette holding the substrates has to be placed precisely within the small region to ensure processing uniformity and repeatability. Moreover, to maintain the steady-state temperature precisely at the intended level and ensure the temperature ramping profiles to be consistent in each magnetic annealing process, a proportional-integral-derivative (PID) controller of the heating system is calibrated based on the thermal load of a particular size of substrates, e.g., 300 mm Si wafers. If any deviation from the anticipated thermal load is sensed in the annealing chamber, the PID controller tends to cause temperature instability which could lead to manufacturing failure. Thus, conventionally, unless the PID controller is recalibrated, the annealing equipment is restricted to processing a particular pre-calibrated size of substrates because loading a different size of substrates and a matching cassette would introduce a substantial thermal load change for which the heater is not calibrated to process. Unfortunately, a recalibration procedure of a PID controller is usually time-consuming, error-prone and can contribute to significant production cost.